Data Access Method for a Timing Controller of a Flat Panel Display and Related Device

ABSTRACT

A data access method for a timing controller of a flat panel display includes forming a line buffer including a plurality of memory cells in the timing controller, dividing the plurality of memory cells into a first section and a second section, wherein the number of memory cells in the first section is greater than the number of memory cells in the second section, writing a first number of pixel data into the first section, wherein the first number of pixel data is included in a plurality of pixel data corresponding to a row of a frame, writing a second number of pixel data into the second section, wherein the second number of pixel data is included in the plurality of pixel data, and the first number is equal to the second number, and reading the plurality of pixel data from the plurality of memory cells according to an order.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a data access method for a timingcontroller of a flat panel display and a related device, and moreparticularly, to a data access method and a related device for reducingmemory cells of a line buffer in the timing controller, for savingmemory cost for displaying images.

2. Description of the Prior Art

The advantages of a liquid crystal display (LCD) include lighter weight,less electrical consumption, and less radiation contamination. LCDmonitors have been widely applied to various portable informationproducts, such as notebooks, mobile phones, PDAs (Personal DigitalAssistants), etc. In an LCD monitor, incident light produces differentpolarization or refraction effects when the alignment of liquid crystalmolecules is altered. The transmission of the incident light is affectedby the liquid crystal molecules, and thus magnitude of the light emittedfrom the liquid crystal molecules varies. The LCD monitor utilizes thecharacteristics of the liquid crystal molecules to control thecorresponding light transmittance and produces gorgeous images accordingto different magnitudes of red, blue, and green light.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a TFT LCDdevice 10 according to the prior art. The TFT LCD device 10 includes apanel 100, a timing controller 102, a data-line-signal output circuit104 and a scan-line-signal output circuit 106. The data-line-signaloutput circuit 104 transforms data signals into voltage signalsaccording to related control signals generated by the timing controller102. The scan-line-signal output circuit 106 controls output states ofthe voltage signals according to related control signals generated bythe timing controller 102, so as to control a potential difference of anequivalent capacitor of each pixel of the panel 100 for grayscaledisplay. In addition, a frame of an image is displayed by rows. As shownin FIG. 1, a row of a frame corresponds to 2N pixel data P₁-P_(2N), andthe 2N pixel data is outputted to the panel 100 via the two portdata-line-signal output circuit 104. That is, the TFT LCD device 10displays the pixel data P₁ and P_(N+1) at the same time, and thendisplays the pixel data P₂ and P_(N+2) at the same time, and so on.

In fact, the original 2N pixel data P₁-P_(2N) does not line up accordingto a displaying order of P₁, P_(N+1), P₂, P_(N+2) . . . , P_(N), andP_(2N). A line buffer 110 located in the timing controller 102 isutilized for transforming an original order of P₁, P₂ . . . , P_(N−1),and P_(N) to the displaying order of P₁, P_(N+1), P₂, P_(N+2) . . . ,P_(N), and P_(2N), and outputting to the two port data-line-signaloutput circuit 104. Please refer to FIG. 2 for a schematic diagram ofthe pixel data P₁-P_(2N) and the line buffer 110. The line buffer 110includes N memory cells, wherein each cell is used for storing twoadjacent pixel data. Therefore, the line buffer 110 can be used forstoring the 2N pixel data P₁-P_(2N). When the pixel data P₁, P₂ . . . ,P_(N), and P_(N+1) are written into the line buffer 110, the pixel dataP₁ and P_(N+1) are read out from the line buffer 110 and outputted tothe data-line-signal output circuit 104. Similarly, when the pixel dataP_(N+2) are written into the line buffer 110, the pixel data P₂ andP_(N+2) are read out from the line buffer 110 and outputted to thedata-line-signal output circuit 104.

However, each memory cell of the line buffer 110 is used for beingwritten and read only once, which cannot enhance the efficiency ofmemory cells.

SUMMARY OF THE INVENTION

It is therefore a primary objective of the claimed invention to providea data access method for a timing controller of a flat panel display anda related device, for saving memory cost for displaying images.

The present invention discloses a data access method for a timingcontroller of a flat panel display, which comprises forming a linebuffer including a plurality of memory cells in the timing controller,dividing the plurality of memory cells into a first section and a secondsection, wherein the number of memory cells in the first section isgreater than the number of memory cells in the second section, writing afirst number of pixel data into the first section, wherein the firstnumber of pixel data is included in a plurality of pixel datacorresponding to a row of a frame, writing a second number of pixel datainto the second section, wherein the second number of pixel data isincluded in the plurality of pixel data corresponding to the row of theframe, and the first number is equal to the second number, and readingthe plurality of pixel data from the plurality of memory cells accordingto an order.

The present invention further discloses a flat panel display for savingmemory cells for displaying images. The flat panel display comprises apanel, a data-line-signal output circuit, a scan-line-signal outputcircuit, and a timing controller. The data-line-signal output circuit iscoupled to the panel and is utilized for outputting pixel data ofimages. The scan-line-signal output circuit is coupled to the panel andis utilized for driving the panel to display the images. The timingcontroller is coupled to the data-line-signal output circuit and thescan-line-signal output circuit and comprises a line buffer, a controlunit and a data packing unit. The line buffer includes a plurality ofmemory cells, wherein the plurality of memory cells is divided into afirst section and a second section, and the number of memory cells inthe first section is greater than the number of memory cells in thesecond section. The control unit is coupled to the line buffer and isutilized for writing a first number of pixel data into the first sectionand writing a second number of pixel data into the second section,wherein the first number of pixel data and the second number of pixeldata are included in a plurality of pixel data corresponding to a row ofa frame. The data packing unit is coupled to the control unit and isutilized for reading the plurality of pixel data from the plurality ofmemory cells according to an order and outputting the plurality of pixeldata to the data-line-signal output circuit.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a TFT LCD device according to the priorart.

FIG. 2 is a schematic diagram of the pixel data P₁-P_(2N) and a buffershown in FIG. 1.

FIG. 3 is a flowchart of a process according an embodiment of thepresent invention.

FIG. 4 is a timing diagram of the process shown in FIG. 3 for writingand reading 16 pixel data.

FIG. 5 is a schematic diagram of a flat panel display according to anembodiment of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 3, which is a flowchart of a process 30 accordingan embodiment of the present invention. The process 30 is utilized for aline buffer in a timing controller of a flat panel display, for savingmemory cost. The process 30 comprises the following steps:

Step 300: Start.

Step 302: Form a line buffer including K memory cells, K>1.

Step 304: Divide the K memory cells into a first section and a secondsection, wherein the number of memory cells in the first section isgreater than the number of memory cells in the second section.

Step 306: Write former N pixel data P₁-P_(N) in 2N pixel data into thefirst section and write latter N pixel data P_(N+1)-P_(2N) in the 2Npixel data into the second section, wherein the 2N pixel datacorresponds to a row of a frame and N>1.

Step 308: Read the 2N pixel data from the K memory cells according to anorder.

Step 310: End.

In the process 30, the pixel data P₁-P_(N) correspond to a former halfof the row of the frame and are written into the first section; and thepixel data P_(N+1)-P_(2N) correspond to a latter half of the row intothe second section and are written into the second section. The numberof memory cells in the first section is greater than the number ofmemory cells in the second section. Therefore, the memory cells in thesecond section are used for being written and read at least twice foroutputting the pixel data P_(N+1)-P_(2N). Note that, the word “former”or “latter” used as above means the output timing of the pixel data.

In the step 306, the step of writing the pixel data P₁-P_(N) into thefirst section involves writing every pair of the pixel data P₁-P_(N)into a corresponding memory cell in the first section. Similarly, thestep of writing the pixel data P_(N+1)-P_(2N) into the second sectioninvolves writing every pair of the pixel data P_(N+1)-P_(2N) into acorresponding memory cell in the second section. Note that, the pixeldata P₁-P_(2N) is outputted to a two port data-line-signal outputcircuit of the flat panel display. Next, in the step 308, the step ofreading the 2N pixel data from the K memory cells according to an orderis reading the pixel data P₁ and P_(N+1) from a corresponding memorycell at the same time, and then reading the pixel data P₂ and P_(N+2)from a corresponding memory cell at the same time, and so on.

Preferably, as a result of the number of memory cells in the firstsection being greater than the number of memory cells in the secondsection, the pixel data P_(N+1)-P_(2N) is further divided into twoportions with the same number of pixel data, a former portionP_(N+1)-P_(3N/2) and a latter portion P_((3N/2)+1)-P_(2N). The pixeldata P_(N+1)-P_(3N/2) are written into the memory cells in the secondsection by every pair of the pixel data, and the pixel dataP_((3N/2)+1)-P_(2N) are also written into the memory cells in the secondsection by every pair of the pixel data. From the above, it is derivedthat a number of the memory cells of the first section is N/2; a numberof the memory cells of the second section is N/4; and the number K ofthe memory cells of the line buffer is equal to N/2+N/4=3N/4.

In the prior art, the 2N pixel data corresponding to a row of a frameare stored in N memory cells. In comparison, the process 30 makes the 2Npixel data corresponding to a row of a frame being stored in 3N/4 memorycells. That is, the embodiment of the present invention saves ¼ numberof memory cells. Note that, the embodiment of the present invention isutilized for writing and reading pixel data corresponding to a row of aframe. The embodiment of the present invention can be used for writingand reading pixel data for displaying a frame.

As to the order for writing the 2N pixel data into the line buffer andreading the 2N pixel data from the line buffer, please refer to FIG. 4.FIG. 4 is a timing diagram of the process 30 for writing and reading 16pixel data. The 16 pixel data P₁-P₁₆ corresponds to a row of a frame andare written into a line buffer including (¾)×8=6 memory cells. Hardlines represent writing actions; dashed lines represent reading actions;W1-W8 represent the writing order of the pixel data; and R1-R8 representthe reading order of the pixel data. In FIG. 4, for example, the pixeldata P₇ and P₈ correspond to W4 and R7 that means that the pixel P₇ andP₈ are the 4th in the writing order and the 7th in the reading order.Note that, the pixel data P₉-P₁₂ and P₁₃-P₁₆ are written into the samememory cells respectively for saving memory cells, so that the pixeldata P₉-P₁₂ have to be read out before the pixel data P₁₃-P₁₆ beingwritten. From the above, a writing and reading order of the 16 pixeldata is: W1→W2→W3→W4→R1→W5→R2→W6→R3→W7→R4→W8→R5→R6→R7→R8. Moreover, theprocess 30 is further utilized for displaying a frame. The writing andreading order of the pixel data for a present row, a previous row and anext row is: . . .R5′→W1→R6′→W2→R7′→W3→R8′→W4→R1→W5→R2→W6→R3→W7→R4→W8→R5→W1″→R6→W2″→R7→W3″→R8→W4″→. . . , wherein R5′-R8′ represent the reading order of the pixel datacorresponding to the previous row, and W1″-W4″ represent the writingorder the pixel data corresponding to the next row.

Please refer to FIG. 5, which is a schematic diagram of a flat paneldisplay 50 according to an embodiment of the present invention. The flatpanel display 50 uses the process 30 to transform an original order ofpixel data to a displaying order of the pixel data, for saving memorycost for displaying images. The flat panel display 50 comprises a panel500, a data-line-signal output circuit 502, a scan-line-signal outputcircuit 504 and a timing controller 506. The data-line-signal outputcircuit 502 is coupled to the panel 500 and is utilized for outputtingthe pixel data of the images. The scan-line-signal output circuit 504 iscoupled to the panel 500 and is utilized for driving the panel todisplay the images. The timing controller 506 is coupled to thedata-line-signal output circuit 502 and the scan-line-signal outputcircuit 504 and comprises a line buffer 510, a control unit 512 and adata packing unit 514. The line buffer 510 includes K memory cellsdivided into a first section and a second section, wherein K>1 and thenumber of memory cells in the first section is greater than the numberof memory cells in the second section. The control unit 512 is coupledto the line buffer 510 and is utilized for writing former N pixel dataP₁-P_(N) into the first section and writing latter N pixel dataP_(N+1)-P_(2N) into the second section, wherein N>1 and the 2N pixeldata P₁-P_(2N) corresponds to a row of a frame. The data packing unit514 is coupled to the control unit 512 and is utilized for reading the2N pixel data in the K memory cells according to an order, andoutputting the 2N pixel data P₁-P_(2N) to the data-line-signal outputcircuit 502.

Please note that, the number of the pixel data P₁-P_(N) is equal to thenumber of the pixel data P_(N+1)-P_(2N), and the number of memory cellsin the second section is less than the number of memory cells in thefirst section, so that the memory cells in the second section are usedfor being written and read at least twice for outputting the pixel dataP_(N+1)-P_(2N). Preferably, the number of memory cells in the firstsection is twice the number of memory cells in the second section. Thedetailed operations of the timing controller 506 are described in theprocess 30 shown in FIG. 3 and are not given here. As a result, thetiming controller 506 writes the 2N pixel data corresponding to a row ofa frame into 3N/4 memory cells and reads the 2N pixel data according tothe order. Compared with the prior art line buffer, the line buffer 510saves ¼ number of memory cells.

In conclusion, the embodiment of the present invention divides thelatter half of the 2N pixel data corresponding to a row of a frame intotwo equal portions, and performs writing and reading actions of thelatter half of the 2N pixel data in the second section of memory cells.Therefore, the embodiment of the present invention uses 3N/4 memorycells for writing and reading the 2N pixel data, which is more efficientthan the prior art using N memory cells, so as to save memory cost fordisplaying images.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention.

1. A data access method for a timing controller of a flat panel displaycomprising: forming a line buffer including a plurality of memory cellsin the timing controller; dividing the plurality of memory cells into afirst section and a second section, wherein the number of memory cellsin the first section is greater than the number of memory cells in thesecond section; writing a first number of pixel data into the firstsection, wherein the first number of pixel data is included in aplurality of pixel data corresponding to a row of a frame; writing asecond number of pixel data into the second section, wherein the secondnumber of pixel data is included in the plurality of pixel datacorresponding to the row of the frame, and the first number is equal tothe second number; and reading the plurality of pixel data from theplurality of memory cells according to an order.
 2. The data accessmethod of claim 1, wherein the number of memory cells in the firstsection is twice the number of memory cells in the second section. 3.The data access method of claim 1, wherein the first number of pixeldata corresponds to a former half of the row of the frame and the secondnumber of pixel data corresponds to a latter half of the row of theframe.
 4. The data access method of claim 1, wherein the step of writingthe first number of pixel data into the first section comprises writingevery pair of the first number of pixel data into a corresponding memorycell in the first section.
 5. The data access method of claim 1, whereinthe step of writing the second number of pixel data into the secondsection comprises: dividing the second number into a third number and afourth number, wherein in the third number is equal to the fourthnumber; writing every pair of the third number of pixel data into acorresponding memory cell in the second section; and writing every pairof the fourth number of pixel data into a corresponding memory cell inthe second section.
 6. The data access method of claim 1, wherein theframe comprises a plurality of rows.
 7. A flat panel display for savingmemory cells for displaying images comprising: a panel; adata-line-signal output circuit coupled to the panel, for outputtingpixel data of the images; a scan-line-signal output circuit coupled tothe panel, for driving the panel to display the images; and a timingcontroller coupled to the data-line-signal output circuit and thescan-line-signal output circuit, the timing controller comprising: aline buffer including a plurality of memory cells, wherein the pluralityof memory cells is divided into a first section and a second section,and the number of memory cells in the first section is greater than thenumber of memory cells in the second section; a control unit coupled tothe line buffer, for writing a first number of pixel data into the firstsection and writing a second number of pixel data into the secondsection, wherein the first number of pixel data and the second number ofpixel data are included in a plurality of pixel data corresponding to arow of a frame; and a data packing unit coupled to the control unit, forreading the plurality of pixel data from the plurality of memory cellsaccording to an order and outputting the plurality of pixel data to thedata-line-signal output circuit.
 8. The flat panel display of claim 7,wherein the number of memory cells in the first section is twice thenumber of memory cells in the second section.
 9. The flat panel displayof claim 7, wherein the first number of pixel data corresponds to aformer half of the row of the frame and the second number of pixel datacorresponds to a latter half of the row of the frame.
 10. The flat paneldisplay of claim 7, wherein the control unit is further utilized forwriting every pair of the first number of pixel data into acorresponding memory cell in the first section.
 11. The flat paneldisplay of claim 7, wherein the control unit is further utilized fordividing the second number into a third number and a fourth number,wherein the third number is equal to the fourth number.
 12. The flatpanel display of claim 11, wherein the control unit is further utilizedfor writing every pair of the third number of pixel data into acorresponding memory cell in the second section, and writing every pairof the fourth number of pixel data into a corresponding memory cell inthe second section.
 13. The flat panel display of claim 7, wherein theframe comprises a plurality of rows.